| A method of redundant clocking detection and power reduction at RT level design.doc |
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| A method of redundant clocking detection and power reduction at RT level design.pdf |
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| A method of redundant clocking detection and power reduction at RT level design.ppt |
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| A method of redundant clocking detection and power reduction at RT level design.txt |
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| A method of redundant clocking detection and power reduction at RT level design.lit |
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| A method of redundant clocking detection and power reduction at RT level design.prc |
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| A method of redundant clocking detection and power reduction at RT level design.pdb |
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| A method of redundant clocking detection and power reduction at RT level design.rb |
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| A method of redundant clocking detection and power reduction at RT level design.chm |
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| Synthesis of low-power asynchronous circuits in a specified environment.doc |
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| Synthesis of low-power asynchronous circuits in a specified environment.pdf |
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| Synthesis of low-power asynchronous circuits in a specified environment.ppt |
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| Synthesis of low-power asynchronous circuits in a specified environment.txt |
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| Synthesis of low-power asynchronous circuits in a specified environment.lit |
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| Synthesis of low-power asynchronous circuits in a specified environment.prc |
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| Synthesis of low-power asynchronous circuits in a specified environment.pdb |
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| Synthesis of low-power asynchronous circuits in a specified environment.rb |
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| Synthesis of low-power asynchronous circuits in a specified environment.chm |
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| Node normalization and decomposition in low power technology mapping.doc |
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| Node normalization and decomposition in low power technology mapping.pdf |
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| Node normalization and decomposition in low power technology mapping.ppt |
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| Node normalization and decomposition in low power technology mapping.txt |
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| Node normalization and decomposition in low power technology mapping.lit |
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| Node normalization and decomposition in low power technology mapping.prc |
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| Node normalization and decomposition in low power technology mapping.pdb |
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| Node normalization and decomposition in low power technology mapping.rb |
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| Node normalization and decomposition in low power technology mapping.chm |
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| Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.doc |
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| Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.pdf |
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| Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.ppt |
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| Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.txt |
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| Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.lit |
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| Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.prc |
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| Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.pdb |
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| Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.rb |
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| Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.chm |
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| Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).doc |
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| Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).pdf |
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| Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).ppt |
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| Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).txt |
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| Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).lit |
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| Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).prc |
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| Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).pdb |
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| Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).rb |
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| Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).chm |
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| Designing SoC's.doc |
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| Designing SoC's.pdf |
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| Designing SoC's.ppt |
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| Designing SoC's.txt |
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| Designing SoC's.lit |
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| Designing SoC's.prc |
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| Designing SoC's.pdb |
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| Designing SoC's.rb |
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| Designing SoC's.chm |
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| Power grid voltage integrity verification.doc |
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| Power grid voltage integrity verification.pdf |
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| Power grid voltage integrity verification.ppt |
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| Power grid voltage integrity verification.txt |
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| Power grid voltage integrity verification.lit |
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| Power grid voltage integrity verification.pdb |
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| Power grid voltage integrity verification.rb |
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| Power grid voltage integrity verification.chm |
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| System level power and performance modeling of GALS point-to-point communication interfaces.doc |
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| System level power and performance modeling of GALS point-to-point communication interfaces.pdf |
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| System level power and performance modeling of GALS point-to-point communication interfaces.ppt |
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| System level power and performance modeling of GALS point-to-point communication interfaces.txt |
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| System level power and performance modeling of GALS point-to-point communication interfaces.lit |
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| System level power and performance modeling of GALS point-to-point communication interfaces.prc |
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| System level power and performance modeling of GALS point-to-point communication interfaces.pdb |
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| System level power and performance modeling of GALS point-to-point communication interfaces.rb |
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| System level power and performance modeling of GALS point-to-point communication interfaces.chm |
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| A low power SRAM using auto-backgate-controlled MT-CMOS.doc |
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| A low power SRAM using auto-backgate-controlled MT-CMOS.pdf |
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| A low power SRAM using auto-backgate-controlled MT-CMOS.ppt |
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| A low power SRAM using auto-backgate-controlled MT-CMOS.txt |
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| A low power SRAM using auto-backgate-controlled MT-CMOS.lit |
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| A low power SRAM using auto-backgate-controlled MT-CMOS.rb |
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| A low power SRAM using auto-backgate-controlled MT-CMOS.chm |
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| Reducing data cache energy consumption via cached load/store queue.doc |
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| Reducing data cache energy consumption via cached load/store queue.pdf |
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| Reducing data cache energy consumption via cached load/store queue.ppt |
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| Reducing data cache energy consumption via cached load/store queue.txt |
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| Reducing data cache energy consumption via cached load/store queue.lit |
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